Generally in computer systems and especially in personal computer systems, data is transferred between various system devices such as a central processing unit (CPU), memory devices, and direct memory access (DMA) controllers. In addition, data is transferred between expansion elements such as input/output (I/O) devices, and between these I/O devices and the various system devices. The I/O devices and the system devices communicate with and amongst each other over computer buses, which comprise a series of conductors along which information is transmitted from any of several sources to any of several destinations. Many of the system devices and the I/O devices are capable of serving as bus controllers (i.e., devices which can control the computer system) and bus slaves (i.e., elements which are controlled by bus controllers).
Personal computer systems having more than one bus are known. Typically, a local bus is provided over which the CPU communicates with cache memory or a memory controller, and a system I/O bus is provided over which system bus devices such as the DMA controller, or the I/O devices, communicate with the system memory via the memory controller. The system I/O bus comprises a system bus and an I/O bus connected by a bus interface unit. The I/O devices communicate with one another over the I/O bus. The I/O devices are also typically required to communicate with system bus devices such as system memory. Such communications must travel over both the I/O bus and the system bus through the bus interface unit.
Typically, one function that a CPU complex contains is that of a cache storage, that stores frequently used data which it reads from various locations in system memory. These cached data are readily available to the CPU without the necessity of frequently going into system memory to fetch the required data, which can be time consuming. Of course, in the case of system memory that can be rewritten with updated or changed data, it is necessary that the CPU complex be "informed" of this rewriting so that any cached data in the CPU complex which corresponds to data which has been rewritten in the memory, and is thus "corrupted, " can be discarded and the new or rewritten data cached, or at least the corrupted data be identified.
This is accomplished by the provision of a snoop/data invalidation function. This function is performed by monitoring the data address and command instructions on the system bus. If at any time this monitoring function detects a write operation to a memory location in system memory which is a location from which the data therein can be cached in the CPU complex, a signal is sent to the CPU complex indicating the address of new data being written into the system memory. This is often referred to as a "positive snoop invalidation". When receiving the signal, the CPU complex can take appropriate action such as discarding the corrupted data and caching the rewritten data.
This technique works well when the write operations to cachable memory are performed on the system bus. However, if the write operation to a memory location is not on the system bus, i.e. it is to a device coupled to the I/O bus, then the snooping function on the system bus can not detect rewritten data to the memory locations; and thus, if data from those locations has been previously cached in the CPU complex, the CPU complex would not "know" that the cached data were corrupted. Such is the case when the memory locations are on devices coupled to the I/O bus, and the rewriting is being performed from a device coupled to the I/O bus and thus never gets put on the system bus. In the absence of a snooping/data invalidate function detecting any rewriting of data into memory, no memory locations coupled to the I/O bus can be cached by the CPU complex, since the CPU complex would never "know" when new data has been written to I/O memory.
Accordingly, it is an object of this invention to provide a technique for providing and indicating cachable memory locations in devices coupled to the I/O bus, allowing memory to be cached in the CPU complex from these identified cachable locations and notifying the CPU complex when data has been written into any cachable memory location from devices coupled to the I/O bus.